1. Field of the Disclosure
The present disclosure relates to electronic devices and processes for forming them, and more particularly to electronic devices including field isolation regions and non-volatile memory and processes for forming the same.
2. Description of the Related Art
Integration of non-volatile memory (“NVM”) arrays into electronic devices, such as integrated circuits, is becoming more difficult as the number of gate dielectric layers present within the electronic device continues to increase. Currently, three or more different gate dielectric layers may be formed. A conventional process sequence includes formation and etching the gate dielectric layers until the last gate dielectric layer has been formed. During this processing sequence, the field isolation regions between active regions are etched multiple times. The field isolation regions are thinned, and corners of the substrate at the field isolation regions become exposed along sides that formerly contacted the field isolation regions. When forming gate electrodes, not all of the gate electrode layer may be removed during patterning, thus resulting in stringers that can form electrical shorts or leakage paths between different transistors that are not to be electrically connected to each other. The corner also creates a point of relatively higher electrical field. Also, the last gate dielectric is typically thinner near the corner than at locations further from the corner. When a subsequently-formed gate electrode is biased, the gate dielectric layer at the corner of the substrate adjacent to the field isolation region may fail at a voltage lower than the designed operating voltage for the transistor.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments.